1. Field of the Invention
This invention relates to an operational circuit to be used for compressing or expanding an amplitude of an alternating current signal with no use of a clock signal.
2. Description of the Prior Art
As a compressing circuit and expanding circuit realizable with MOS type integrated circuit, such a circuit that is provided with an analog operational circuit using a .DELTA..SIGMA. modulation circuit and a rectifying and averaging circuit has been proposed previously, an example of which is disclosed in the Japanese Laid-Open Patent Publication No. 2-138609. The circuit thus disclosed has an analog operational circuit which comprises a .DELTA..SIGMA. modulation circuit composed of an A/D converter circuit and a first D/A converter circuit, a second D/A converter circuit and a low-pass filter.
An analog signal to be processed is converted through the A/D converter circuit of the .DELTA..SIGMA. modulation circuit into a digital signal in response to a clock signal and sent to the first D/A converter circuit. The digital signal is converted through the first D/A converter circuit into a first analog signal which takes a positive or negative value in response to a first reference signal and fed back to the A/D converter circuit as a differential input.
The digital signal outputted from the A/D converter circuit is also sent to the second D/A converter circuit to be converted into a second analog signal which takes a positive or negative value in response to a second reference signal and sent to the low-pass filter.
If at least one of the first and second reference signals is made an operational signal, an analog signal is outputted from the low-pass filter as the result of operation.
The first and second D/A converter circuits and the low-pass filter are made, for example, of a switched capacitor and an operational amplifier.
Such an expanding circuit that comprises the conventional operational circuit as explained above and a rectifying and averaging circuit is disclosed in FIG. 7 of the above-mentioned patent publication. The rectifying and averaging circuit comprises a rectifying circuit and an averaging circuit. As the rectifying circuit, for example, a full-wave or half-wave rectifier using a diode can be employed. The averaging circuit can be made, for example, of an operational amplifier having a feedback capacitor and a resistor. Besides, the rectifying and averaging circuit may be composed, for example, of a switched capacitor, a comparator and an operational amplifier.
With the conventional expanding circuit as explained above, an alternating current (AC) signal V.sub.IN to be processed is delivered to the .DELTA..SIGMA. modulation circuit of the analog operational circuit and the rectifying and averaging circuit. Here, if a signal obtained by rectifying the signal V.sub.IN is expressed as .vertline.V.sub.IN .vertline., and a signal obtained by averaging the same is expressed as [.vertline.V.sub.IN .vertline.], the signal [.vertline.V.sub.IN .vertline.] thus obtained by rectifying and averaging the signal V.sub.IN is sent to the second D/A converter circuit as the second reference signal. The analog operational circuit computes the product of the signals .vertline.V.sub.IN .vertline. and [.vertline.V.sub.In .vertline.], or K.sub.1 .multidot.V.sub.IN .multidot.[.vertline.V.sub.IN .vertline.] (K.sub.1 is a constant) to output as an analog signal V.sub.OUT through the low-pass filter.
Namely, if EQU V.sub.IN =X.multidot. sin .omega.t
where X is an amplitude, .omega. is an angular velocity and t is a time, the input signal [.vertline.V.sub.IN .vertline.] can be expressed as follows; .OJOFF[.vertline.V.sub.IN .vertline.]=K.sub.2 .multidot.X where K.sub.2 is a constant. Hence EQU V.sub.OUT =K.sub.1 .multidot.V.sub.IN .multidot.[.vertline.V.sub.IN .vertline.]=K.sub.1 .multidot.K.sub.2 .multidot.X.sup.2 .multidot. sin .omega.t
This means that an AC signal whose amplitude is expanded to (K.sub.1 .multidot.K.sub.2 .multidot.X.sup.2) can be obtained.
Such a compressing circuit that comprises the conventional operational circuit and a rectifying and averaging circuit is disclosed in FIG. 8 of the above-mentioned patent publication. The rectifying and averaging circuit used in this compressing circuit is the same as that of the expanding circuit already shown above.
With this conventional compressing circuit, the AC signal V.sub.IN to be processed is inputted to the .DELTA..SIGMA. modulation circuit of the analog operational circuit and sent through the low-pass filter to the rectifying and averaging circuit as the analog signal V.sub.OUT. Here, if a signal obtained by rectifying the signal V.sub.OUT is expressed as .vertline.V.sub.OUT .vertline. and a signal obtained by averaging the signal .vertline.V.sub.OUT .vertline. is expressed as [.vertline.V.sub.OUT .vertline.], the signal [.vertline.V.sub.OUT .vertline.] as the output signal of the rectifying and averaging circuit is sent to the first D/A converter circuit as the first reference signal. The analog operational circuit computes the quotient of the signals V.sub.IN and [.vertline.V.sub.OUT .vertline.], or K.sub.3 .multidot.V.sub.IN /[.vertline.V.sub.OUT .vertline.] (K.sub.3 is a constant) to output from the low-pass filter as the analog signal V.sub.OUT.
Namely, if EQU V.sub.IN =X.multidot.sin .omega. t EQU V.sub.OUT =Y.multidot.sin .omega. t
where Y is an amplitude, the output signal [.vertline.V.sub.OUT .vertline.] can be expressed as follows; EQU [.vertline.V.sub.OUT .vertline.]=K.sub.4 .multidot.Y EQU V.sub.OUT =(K.sub.3 .multidot.V.sub.IN)/[.vertline.V.sub.OUT .vertline.]=(K.sub.3 .multidot.V.sub.IN)/(K.sub.4 .multidot.Y)
where K.sub.4 is a constant. Hence EQU Y=(K.sub.3 /K.sub.4).sup.1/2 .multidot.X.sup.1/2
Therefore EQU V.sub.OUT =(K.sub.3 /K.sub.4).sup.1/2 .multidot.X.sup.1/2 .multidot.sin .omega. t
This means that an AC signal whose amplitude is compressed to {(K.sub.3 /K.sub.4).sup.1/2 .multidot.X.sup.1/2 } can be obtained.
With the conventional expanding and compressing ucircuits shown above, however, a clock signal is employed and as a result, there is such a problem that it is difficult to obtain a compressed signal or expanded signal having a good signal-to-noise ratio due to the effects of a clock noise.
In addition, the .DELTA..SIGMA. modulation circuit or switched capacitor type rectifying and averaging circuit becomes large in circuit scale and as a result, there arises such a problem that semiconductor integrated circuits to be used are unavoidably large in chip size as well as increased in power consumption.